Introduction
Here I implemented a 2-bit adder using 1-bit full adder and a 1-bit half adder (Figure 1) as components that are connected in the top-level module and also I described both its components in VHDL. I also prepared two implementations where VHDL components are instantiated in:
- · VHDL top-level file and
- · Block Design top-level file
After which I simulated and implemented each project on FPGA development board.
Workflow
Throughout the design stage, I had followed some sequential flow that is necessary for carrying out this task using “vivado IDE”. Followings are the steps I took:
1. IMPLEMENTATION OF HALF_ADDER SOURCE FILE
1.2. I defined module for the input and output of the source file by given names to the ports.
1.3. I started building my architecture behavior for the entity right under the keyword “begin” such as:
architecture Behavioral of half_adder_beh is
begin
sum0 <= (a0 xor b0)
carry <= a0 and b0;
end Behavioral;
Below shows the truth table of half adder which can be formulated with two different logic gates XOR and AND.
Figure 2: Half Adder Truth Table
A
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B
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CARRY
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SUM
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0
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0
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0
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0
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1
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0
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0
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1
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0
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1
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0
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1
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1
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1
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1
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0
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2. IMPLEMENTATION OF FULL_ADDER SOURCE FILE
2.1. I created a new source file for “Full_adder_beh” entity
2.2. I defined the module for the input and output of the source file by given names to the ports.
2.3. I build the architecture behavior for the entity right under the keyword “begin” such as:
architecture Behavioral of full_adder_beh is
begin
carry_out <=(a1 and b1) OR (a1 and carry_in) OR (b1 and carry_in);
sum1<= (a1 xor b1) xor carry_in;
end Behavioral;
Below shows the truth table of the full adder.
A
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B
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CARRY_IN
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CARRY_OUT
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SUM
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0
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0
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0
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0
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0
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0
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0
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1
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0
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1
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0
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1
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0
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0
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1
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0
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1
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1
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1
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0
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1
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0
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0
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0
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1
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1
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0
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1
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1
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0
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1
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1
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0
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1
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0
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1
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1
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1
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1
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1
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3. IMPLEMENTATION OF 2 BIT ADDER
3.1. I created a new source file for “twoBit adder” entity
3.2. I defined the module for the input and output of the source file by given names to the ports.
3.3. I started port mapping for the components right under the keyword “begin”:
architecture Behavioral of two_bit_adder is
component half_adder
Port ( a0 : in STD_LOGIC;
b0 : in STD_LOGIC;
carry :out STD_LOGIC;
sum0 :out STD_LOGIC);
end component;
component full_adder
Port(a1 :in STD_LOGIC;
b1 :in STD_LOGIC;
carry_in :in STD_LOGIC;
sum1 :out STD_LOGIC;
carry_out :out STD_LOGIC);
end component;
signal join_adders : std_logic;
begin
C1: component half_adder port map (a0=>A0, b0=>B0, carry=>join_adders, sum0=>SUM0);
C2: component full_adder port map(a1=>A1, b1=>B1, carry_in=>join_adders, carry_out=>CARRY_OUT, sum1=>SUM1);
end Behavioral;
The code before the keyword “begin” was to do the encapsulation, so as to simulate the 2-bit adder. the 2-bit adder holds 1 half adder and then 1 full adder as well.
Therefore the structural behaviour of 2-bit-adder is shown below:
C1: component half_adder port map (a0=>A0, b0=>B0, carry=>join_adders, sum0=>SUM0);
C2: component full_adder port map(a1=>A1, b1=>B1, carry_in=>join_adders, carry_out=>CARRY_OUT, sum1=>SUM1);
In these cases above:
C1 = represent the component that consists of half_ adder_beh port mapping
C2 = represent the component that consists of full_adder_beh port mapping; full adder (Figure 6) can be seen as a logical block that consists of 3 half adders connected to each other.
The purpose of port mapping within the architecture is to associate signals with ports on components; in this case, is used for interconnections between components.
A0
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A1
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B0
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B1
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SUM0
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SUM1
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CARRY
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0
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0
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0
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0
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0
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0
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0
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0
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0
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0
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1
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0
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1
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0
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0
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0
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1
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0
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1
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0
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0
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0
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0
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1
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1
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1
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1
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0
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0
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1
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0
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0
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0
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1
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0
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0
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1
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0
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1
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0
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0
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1
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0
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1
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1
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0
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1
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1
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0
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0
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1
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1
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1
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1
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0
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1
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1
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0
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0
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0
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1
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0
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0
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1
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0
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0
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1
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1
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1
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0
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1
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0
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1
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0
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0
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1
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0
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1
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0
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1
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1
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0
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0
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1
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1
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1
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0
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0
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1
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1
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0
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1
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1
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0
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1
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1
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0
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1
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1
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1
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1
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0
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0
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0
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1
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1
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1
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1
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1
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0
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1
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1
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2-BIT-ADDER TRUTH TABLE
4. CREATING ADDER BLOCK DESIGN
The Adder Block Diagram was created using the IP Integrator flow section by selecting “Create Block Diagram” option in the Flow Navigator.
Figure 4: Adder Block Design
TESTBENCH:
The test bench stimulus process help to show the logical behavior of how my code operates without been tested on FPGA board. It actually encapsulates the behavioral port of my source file as a component. it also permits signal declaration. Mapping its declared signal with the encapsulated component of the behavioral source file values for input and output is possible right within its unit under test. Right under the keyword “begin” situated within the stimulus, the assignment of digit values to signals begins. On the other hand the keyword “wait” stop the test indefinitely whereas the “wait for” is used to wait for a specific period of time before the continuation of the next stimulus process. The stimuli process assigns all possible input combinations, which therefore permit outputs comparation to each row of the truth table.
Therefore, the correctness of the 2-bit-adder was carried out by this stimulus waveform which was implemented by testbench code and compared with the 2 bit adder truth table
Figure 5: Simulation waveform
The design below shows the full diagram of the RTL design of the 2-bit-adder
Figure 6: RTL design of 2-bit-adder
CONCLUSION
Adder operation is performed using vivado 2018.2 version. The ideal about adder is that it takes the number of inputs thus providing 3 output SUM0, SUM1 AND CARRY.
An adder is a digital circuit that performs additions of numbers and it’s used in arithmetic logic units.
In addition, the source code was compiled and simulated to verify the correctness of the program instruction. Upon completion of the tasks, I have shown how to implement the structural design using components as connections to generate a fully operating system like an adder.
cool
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